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1 ds05-10196-1e fujitsu semiconductor data sheet memory cmos 4m 4 bit hyper page mode dynamic ram mb8117405a-60/-70 cmos 4,194,304 4 bit hyper page mode dynamic ram n description the fujitsu mb8117405a is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 4-bit increments. the mb8117405a features a ?yper page mode of operation whereby high- speed random access of up to 1,024-bits of data within the same row can be selected. the mb8117405a dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb8117405a is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb8117405a is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb8117405a are not critical and all inputs are ttl compatible. n product line & features parameter mb8117405a-60 MB8117405A-70 ras access time 60 ns max. 70 ns max. randam cycle time 104 ns min. 124 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. hyper page mode cycle time 25 ns min. 30 ns min. low power dissipation operating current 577.5 mw max. 495 mw max. standby current 11 mw max. (ttl level)/5.5 mw max. (cmos level) this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 4,194,304 words 4 bit organization silicon gate, cmos, advanced capacitor cell all input and output are ttl compatible 2048 refresh cycles every 32.8ms early write or oe controlled write capability ras only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance
2 mb8117405a-60/MB8117405A-70 n absolute maximum ratings (see note.) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7 v voltage of v cc supply relative to v ss v cc ?.5 to +7 v power dissipation p d 1.0 w short circuit output current i out ?0 to +50 ma operating temperature t ope 0 to +70 c storage temperature t stg ?5 to +125 c plastic tsop package (fpt-26p-m05) package and ordering information ?26-pin plastic (300mil) soj, order as mb8117405a-xxpj ?26-pin plastic (300mil) tsop-ii with normal bend leads, order as mb8117405a-xxpftn plastic soj package (lcc-26p-m09) marking side
3 mb8117405a-60/MB8117405A-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a 0 toa 10 c in1 ?pf input capacitance, ras , cas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 4 c dq ?pf fig. 1 ? mb8117405a dynamic ram - block diagram dq 1 to dq 4 v cc v ss a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 clock gen #1 write clock gen mode control clock gen #2 column decoder sense ampl & i/o gate 16,777,216 bit storage cell data in buffer data out buffer address buffer pre- decoder refresh address counter row decoder substrate bias gen & cas ras we oe a 10
4 mb8117405a-60/MB8117405A-70 n pin assignments and descriptions v cc dq 1 dq 2 we ras n.c. 26-pin soj: (top view) 1 2 3 4 5 19 14 15 8 9 10 11 12 26 25 24 23 22 17 16 621 13 18 1 2 3 4 5 8 9 10 11 12 15 16 17 26 25 24 23 22 19 18 6 13 14 21 (marking side) 1 pin index a 10 a 0 a 1 a 2 a 3 v cc v ss dq 4 dq 3 cas oe a 9 a 8 a 7 a 6 a 5 a 4 v ss v cc dq 1 dq 2 we ras n.c. a 10 a 0 a 1 a 2 a 3 v cc v ss dq 4 dq 3 cas oe a 9 a 8 a 7 a 6 a 5 a 4 v ss 26-pin fpt: (top view) designator function v cc a 0 to a 10 v ss data input/ output write enable. row address strobe. address inputs. +5 volt power supply. column address strobe. circuit ground. output enable. we ras cas oe n.c. no connection dq 1 to dq 4
5 mb8117405a-60/MB8117405A-70 n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20ns are acceptable. n functional operation address inputs twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. since only twelve address bits (a 0 to a 10 ) are available, the row and column inputs are separately strobed by ras and cas as shown in figure 1. first, twelve row address bits are input on pins a 0 -through-a 10 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edge of ras and cas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min.)+ t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways : an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data (dq 1 -dq 4 ) is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max.) is satis?d. t cac : from the falling edge of cas when t rcd is greater than t rcd (max.). t aa : from column address inpit when t rad is greater than t rad (max.), and t rcd (max.) is satis?d. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . t oez : from oe inactive. t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and cas are inactive, or cas is reactived. when an early write is execute, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. spply voltage v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs/ outputs * v il ?.3 0.8 v 1 1 1
6 mb8117405a-60/MB8117405A-70 hyper page mode of operation the hyper page mode of operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (with column address locations), any of 1,024-bits can be accessed and, when multiple mb8117405as are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated.
7 mb8117405a-60/MB8117405A-70 n dc characteristics (recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol conditions value unit min. typ. max. output high voltage v oh i oh = ? ma 2.4 v output low voltage v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in 5.5 v; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins under test = 0 v ?0 10 m a output leakage current i o(l) 0 v v out 5.5 v; data out disabled ?0 10 operating current (average power supply current) mb8117405a-60 i cc1 ras & cas cycling; t rc = min. ma MB8117405A-70 standby current (power supply current) ttl level i cc2 ras = cas = v ih ma cmos level ras = cas 3 v cc ?.2 v refresh current#1 (average power supply current) mb8117405a-60 i cc3 cas = v ih , ras cycling; t hpc = min. ma MB8117405A-70 hyper page mode current mb8117405a-60 i cc4 ras = v il , cas cycling; t hpc = min. ma MB8117405A-70 refresh current#2 (average power supply current) mb8117405a-60 i cc5 ras cycling; cas -before-ras ; t rc = min. ma MB8117405A-70 1 1 2 105 90 2.0 1.0 2 105 90 2 105 90 2 105 90
8 mb8117405a-60/MB8117405A-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb8117405a-60 MB8117405A-70 unit min. max. min. max. 1 time between refresh t ref 32.8 32.8 ms 2 random read/write cycle time t rc 104 124 ns 3 read-modify-write cycle time t rwc 138 162 ns 4 access time from ras t rac ?0?0ns 5 access time from cas t cac ?5?7ns 6 column address access time t aa ?0?5ns 7 output hold time t oh 3?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time t off ?5?7ns 11 output buffer turn off delay time from ras t ofr ?5?7ns 12 output buffer turn off delay time from we t wez ?5?7ns 13 transition time t t 150150ns 14 ras precharge time t rp 40?0ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 15?7ns 17 cas to ras precharge time t crp 5?ns 18 ras to cas delay time t rcd 14 45 14 53 ns 19 cas pulse width t cas 10?3ns 20 cas hold time t csh 40?0ns 21 cas precharge time (normal) t cpn 10?0ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 10?0ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 10?0ns 26 column address hold time from ras t ar 24?4ns 27 ras to column address delay time t rad 12 30 12 35 ns 28 column address to ras lead time t ral 30?5ns 29 column address to cas lead time t cal 23?8ns 30 read command set up time t rcs 0?ns 31 read command hold time referenced to ras t rrh 0?ns 32 read command hold time referenced to cas t rch 0?ns 33 write command set up time t wcs 0?ns 34 write command hold time t wch 10?0ns 35 write hold time from ras t wcr 24?4ns 6, 9 7, 9 8, 9 10 10 10 21 11, 12, 22 19 13 14 14 15, 20
9 mb8117405a-60/MB8117405A-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb8117405a-60 MB8117405A-70 unit min. max. min. max. 36 we pulse width t wp 10?0ns 37 write command to ras lead time t rwl 15?7ns 38 write command to cas lead time t cwl 10?3ns 39 din set up time t ds 0?ns 40 din hold time t dh 10?0ns 41 data hold time from ras t dhr 24?4ns 42 ras to we delay time t rwd 77?9ns 43 cas to we delay time t cwd 32?6ns 44 column address to we delay time t awd 47?4ns 45 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 46 cas set up time for cas -before-ras refresh t csr 0?ns 47 cas hold time for cas -before-ras refresh t chr 10?2ns 48 access time from oe t oea ?5?7ns 49 output buffer turn off delay from oe t oez ?5?7ns 50 oe to ras lead time for valid data t oel 10?0ns 51 oe to cas lead time t col 5?ns 52 oe hold time referenced to we t oeh 5?ns 53 oe to data in delay time t oed 15?7ns 54 ras to data in delay time t rdd 15?7ns 55 cas to data in delay time t cdd 15?7ns 56 din to cas delay time t dzc 0?ns 57 din to oe delay time t dzo 0?ns 58 din to oe delay time t oep 8?ns 59 oe hold time referenced to cas t oech 10?0ns 60 we precharge time t wpz 8?ns 61 we to date in delay time t wed 15?7ns 62 hyper page mode ras pulse width t rasp 100000 100000 ns 63 hyper page mode read/write cycle time t hpc 25?0ns 64 hyper page mode read-modify-write cycle time t hprwc 69?9ns 65 access time from cas precharge t cpa ?5?0ns 66 hyper page mode cas precharge time t cp 10?0ns 67 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 68 hyper page mode cas precharge to we delay time t cpwd 52?9ns 20 20 20 9 10 16 17 17 9, 18
10 mb8117405a-60/MB8117405A-70 notes: 1. referenced to v ss . 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il , cas = v ih and v il > ?.3 v. i cc1 , i cc3 , i cc4 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc2 is speci?d during ras =v ih and v il > ?.3 v. 3. an initial pause (ras = cas =v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. 4. ac characteristics assume t t = 2ns. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min.) and v il (max.). 6. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd is greater than the maximum recomended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. 7. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 8. if t rcd 3 t rcd (max.) and t asc t aa ?t cac ?t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 50 pf. 10. t off and t oez is speci?d that output buffer change to high impedance state. 11. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min.) = t rah (min.)+ 2t t + t asc (min.). 13. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 16. assumes that t wcs < t wcs (min.). 17. either t dzc or t dzo must be satis?d. 18. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max.). 19. assumes that cas -before-ras refresh. 20. t wcs , t cwd , t rwd and t awd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs > t wcs (min.), the cycle is an early write cycle and dout pin will maintain high impedance state thoughout the entire cycle. if t cwd > t cwd (min.), t rwd > t rwd (min.) , and t awd > t awd (min.), the cycle is a read modify-write cycle and data from the selected cell will appear at the dout pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the dout pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations. 21. the last cas rising edge. 22. the ?st cas falling edge.
11 mb8117405a-60/MB8117405A-70 n functional truth table x: ? or ? *: it is impossible in hyper page mode operation mode clock input address input data refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes * t rcs 3 t rcs (min.) write cycle (early write) l l l x valid valid valid high-z yes * t wcs 3 t wcs (min.) read-modify- write cycle llh ? ll ? h valid valid valid valid yes * ras -only refresh cycle l h x x valid high-z yes cas -before- ras refresh cycle l l h x high-z yes t csr 3 t csr (min.) hidden refresh cycle h ? llh ? x l valid yes previous data is kept. fig. 4 ? t cpa vs. t cp t rac (ns) t rcd (ns) t rad (ns) t cp (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad t rac (ns) t cpa (ns) 100 90 80 70 60 20 30 40 50 60 70 50 60ns version 70ns version 100 90 80 70 60 50 70ns version 60ns version 20 30 40 50 60 70 60ns version 70ns version 70 60 50 40 30 20 10 20 30 40 50 60
12 mb8117405a-60/MB8117405A-70 row add valid data high-z high-z column add ? or ? description to implement a read operation, a valid address is latched in by the ras and cas and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max.), access time = t cac . if t rad > t rad (max.), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea however, if either cas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. fig. 5 ? read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe t rc t ras t crp t csh t rcd t rsh t cas t rp t rad t asr t rah t asc t cah t ral t cal t cdd t rdd t oel t col t rcs t rrh t rch t wpz t aa t cac t rac t dzc t on t oea t dzo t on t oh t oed t wed t wez t oh t off t oez
13 mb8117405a-60/MB8117405A-70 row valid data i n add column add high-z cas ? or ? description a write cycle is similar to a read cycle except we is set to a low state and oe is a ? or ? signal. a write cycle can be implemented in either of three ways?arly write, oe write (delayed write), or read-modify-write. during all write cycles, timing parameters t rwl , t cwl and t ral must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pin is latched with the falling edge of cas and written into memory. fig. 6 ? early write cycle (oe = ? or ?? ras a 0 to a 10 we dq (input) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq (output) t rc t ras t csh t rp t rsh t rcd t crp t cas t ar t asr t rah t asc t cah t wcr t wcs t wch t dhr t ds t dh t rad
14 mb8117405a-60/MB8117405A-70 valid data i n col row add add high-z high-z high-z ? or ? invalid data description in the oe (delayed write) cycle, t wcs is not satis?d ; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t ds ). fig. 7 ? delayed write cycle (oe control) v ih v il v ih v ih v ih v il v ih v il v ih v il v ih v il ras a 0 to a 10 we dq (input) oe v oh v ol dq (output) cas t rc t ras t crp t rp t csh t cas t rsh t rcd t asr t rah t asc t cah t rcs t wch t cwl t rwl t wp t ds t dh t dzc t oed t on t dzo t on t oez t oeh t ar
15 mb8117405a-60/MB8117405A-70 valid data i n col row add add high-z high-z valid high-z cas fig. 8 ? read-write/read-modify-write-cycle v ih v il v ih v il v ih v il v ih v il v oh v ol ras we a 0 to a 10 dq (output) ? or ? description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. v ih v il dq (input) v ih v il oe t rp t rwc t ras t ar t crp t rcd t rad t asr t rah t asc t cah t rwd t cwl t rwl t awd t cwd t rcs t dzc t rac t ds t wp t dh t oeh t oed t cac t aa t on t oh t oea t dzo t oez
16 mb8117405a-60/MB8117405A-70 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rasp t crp t asr t asc t rcs t rhcp t rp t rcd t cas t rsh t hpc t cas t cas t cp t rch t rcs t rch t rcs t dzc t cpa t cah t ar t cah t rah t asc t rrh t cah t asc t rch t on t cac t on t aa t rad t csh t ral high-z t dzo t aa high-z t rac t rdd t oh t off t oed t cpa t oh t on t ohc t cac t ohc t ofr t cdd t oez t oh valid data out valid data out valid cas description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 9 ? hyper page mode read cycle ras a 0 to a 10 we dq (input) dq (output) oe ? or ? during one cycle is achieved in hyper-page mode, the input/output timing apply the same manner as the former cycle. row add col add col add col add
17 mb8117405a-60/MB8117405A-70 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rasp t crp t asr t asc t rcs t rhcp ? or ? t rp t cas t rsh t hpc t cas t cp t cah t cah t rah t asc t rrh t cah t asc t rch t cac t csh t ral high-z t ofr t off t oh t oez t oed t cac t rdd t oh t oh t aa t cpa t cpa t cac t aa t on t oea t oech t oep t oh t oea t rac t cp t cdd t ar t col t oea t cal t oh t oez t oez high-z t rad col t dzc t ohc t cas t rcd t aa t dzo valid data out valid data out valid data out t on valid output cas fig. 10 ? hyper page mode read cycle (oe control) ras a 0 to a 10 we dq (input) dq (output) description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. to obtain a high impedance state, set oe or both ras and cas going high level. oe during one cycle is achieved in hyper-page mode, the input/output timing apply the same manner as the former cycle. row add col add col add
18 mb8117405a-60/MB8117405A-70 cas fig. 11 ? hyper page mode read cycle (we control) ras a 0 to a 10 we dq (input) dq (output) description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. to obtain a high impedance state, con?m either of the following conditions, oe set to a high level or we set to a low level after cas set to a high level or ras and cas set to a high level. oe ? or ? during one cycle is achieved in hyper-page mode, the input/output timing apply the same manner as the former cycle. v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rasp t crp t asr t asc t rcs t rhcp t rp t cas t rsh t hpc t cas t cas t dzc t cah t cah t asc t cah t asc t rch t cac t aa t csh t ral high-z t off t oh t rdd t oh t oh t aa t cac t aa t oea t dzo t on t rac t ofr t rcs t rch t wpz t rch t cal t wez t on t on t wez t wpz t cdd t wed t wez t on t ar t rcs t wpz t rcd v oh v ol col add t cac t oed t oez t rah t rad valid valid data out valid data out high-z row add col add col add
19 mb8117405a-60/MB8117405A-70 high-z valid data i n valid data i n valid data i n col row add add col add col add cas fig. 12 ? hyper page mode early write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 10 we dq (input) v oh v ol dq (output) ? or ? description the hyper page mode write cycle is executed in the same manner as the hyper page mode read cycle except the states of we and oe are reversed. data appearing on the dq pins is latched on the falling edge of cas and written into memory. during the hyper page mode write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. t rasp t rp t rhcp t cas t csh t crp t rcd t cas t pc t cah t ral t asc t cah t asc t asc t cah t ar t rah t asr t wcr t wcs t cwl t wch t wcs t cwl t wch t wch t wcs t cwl t rwl t dh t ds t dh t ds t ds t dh t dhr t rsh t cp
20 mb8117405a-60/MB8117405A-70 valid valid col add col add row add data i n data i n high-z cas description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 13 ? hyper page mode delayed write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il we dq (input) v oh v ol dq (output) v ih v il oe ? or ? t rasp t rp t hpc invalid data t rsh t cas t cas t cp t csh t rcd t crp t asr t rah t ar t asc t cah t asc t cah t cwl t rwl t wch t wp t cwl t wch t rcs t wp t dzc t ds t dh t dh t ds t oed t on t on t oed t on t dzo t oez t on t oez t oeh a 0 to a 10 t oeh
21 mb8117405a-60/MB8117405A-70 valid col add col add high-z row add col add high-z data i n high-z valid data out valid data out cas fig. 14 ? hyper page mode read/write mixed cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 10 we dq (input) v oh v ol dq (output) v ih v il oe description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min.) is invalid. ? or ? t rasp t csh t cas t rad t crp t cas t cas t rcd t rp t rsh t asr t rah t cah t asc t cah t asc t rhcp t asc t cah t cal t ral t hpc t cp t rac t rch t wed t wch t rcs t wcs t dzc t ds t dh t cac t ohc t aa t cpa t cac t oed t wez t aa t oez t on t oea t on t dzo t cal t ar
22 mb8117405a-60/MB8117405A-70 col add col add high-z row add valid data i n valid data i n cas fig. 15 ? hyper page mode read modify write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il a 0 to a 10 we dq (input) v oh v ol dq (output) v ih v il oe ? or ? description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. t rasp t rp t crp valid data t rcd t cwd t rwl t hprwc t cwd t cp t asc t cah t asc t cah t rad t rah t asr t rcs t awd t cpwd t cwl t rcs t cwl t wp t wp t ds t dh t dh t ds t rwd t dzc t oed t cac t aa t on t on t aa t cac t oed t on t on t rac t dzo t oea t cpa t oez t oea t oeh t oez t ar t oeh
23 mb8117405a-60/MB8117405A-70 high-z high-z row address ? or ? cas cas fig. 16 ? ras -only refresh (we = oe = ? or ?? fig. 17 ? cas -before-ras refresh (adress = we = oe = ? or ?? v ih v il ras v ih v il v ih v il v oh v ol a 0 to a 10 v ih v il v oh v ol v ih v il ras dq (output) description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32.8-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, d out pin is kept in a high-impedance state. description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep- aration for the next cas -before-ras refresh operation. dq (output) t ras t rc t rp t rpc t crp t rah t asr t crp t off t oh t rc t rp t ras t cpn t csr t chr t rpc t csr t cpn t off t oh
24 mb8117405a-60/MB8117405A-70 column row address address valid data out high-z high-z cas fig. 18 ? hidden refresh cycle v ih v il ras v ih v il v ih v il v ih v il v oh v ol a 0 to a 10 we v ih v il v ih v il dq (output) oe ? or ? description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. dq (input) t rc t ras t ras t rc t rp t oel t rcd t rsh t rad t chr t rp t crp t rah t asr t asc t ral t cah t rcs t rrh t aa t rac t cac t dzc t cdd t off t oh t ofr t dzo t oea t on t oez t oed t ar
25 mb8117405a-60/MB8117405A-70 high-z high-z high-z valid data in column address cas fig. 19 ? cas -before-ras refresh counter test cycle parameter unit min. max. ns no. min. max. 55 50 (at recommended operating conditions unless otherwise noted.) symbol 35 ns 35 71 72 73 77 ns 70 99 ns 90 99 ns 90 mb8117405a-60 MB8117405A-70 access time from cas column address hold time cas to we delay time cas pulse width ras hold time note. assumes that cas -before-ras refresh counter test cycle only.. v ih v il v ih v il ras a 0 to a 10 v ih v il v ih v il v ih v il v ih v il v ih v il we dq (input) oe 70 69 t fcac t fcah t fcwd t fcas t frsh ? or ? valid data out description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 10 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 10 are de?ed by latching levels on a 0 -a 10 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 2048 row addresses at the same column address by using normal write cycles. 4) read ? written in procedure 3) and check; simultaneously write ? to the same addresses by using cas -before-ras refresh counter test (read-modify-write cycles). repeat this procedure 2048 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) t frsh t rp t chr t csr t cp t fcas t fcah t asc t rcs t cwl t rwl t wp t ds t dh t dzc t oed t oeh t oez t on t dzo t fcwd t fcac t oea
26 mb8117405a-60/MB8117405A-70 n package dimensions (suf?: -pj) c 1994 fujitsu limited c26059s-3c-1 "a" lead no. 2.80(.110)nom 0.64(.025)min 15.24(.600)ref 17.150.13(.675.005) (.050.005) 1.270.13 26 21 19 14 1 68 13 7.62 (.300) nom 8.600.13 (.339.005) index .008 +.002 ?.001 +0.05 ?0.02 0.20 6.860.25 (.270.010) .138 ?.008 +.010 ?0.20 +0.25 3.50 r0.81(.032)typ 2.60(.102)nom 0.10(.004) (.017.004) 0.430.10 0.81(.032)max details of "a" part * 26 pin, plastic soj (lcc-26p-m09) dimensions in mm(inches).
27 mb8117405a-60/MB8117405A-70 n package dimensions (continued) (suf?: -pftn) 1.150.05(.045.002) lead no. (.005.002) 0.1250.05 8.220.20 (.324.008) (.020.004) 0.500.10 (.363.008) 9.220.20 (.300.004) 7.620.10 (stand off) 0.05(.002)min * 0.21(.008) m ref 15.24(.600) 0.10(.004) typ 1.27(.050) (.675.004) 17.140.10 (.016.004) 0.400.10 details of "a" part 0.25(.010) 0.15(.006) max 0.50(.020) max 0.15(.006) index "a" 1 6 8 13 14 19 21 26 1994 fujitsu limited f26005s-2c-1 c 26 pin, plastic tsop(ii) (fpt-26p-m05) dimensions in mm(inches).
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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